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实习项目


Perl 脚本

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 #!/usr/bin/perl my $value; $value = open(file1, "< synth.log"); if ($value) { print "file open successfully!\n"; } else { die ...

Design Compiler Synthesis SDC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67...

Sequence Detector

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69...

Asynchronous FIFO

Reference: https://www.cnblogs.com/mikewolf2002/p/10945488.html 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46...

Synchronous FIFO

Reference: https://www.youtube.com/watch?v=GSPIRcBQUVo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49...

how to fix setup and hold violations?

Reference: fixing-setup-violations fixing-hold-violations STC: max delay in data path; min delay in clock path HTC: min delay in data path; max delay in clock path 前六种方法是相对应的 How...

IC Related Links

Wonderful Blog Sites: TeamVLSI vlsiuniverse Verilog Practice Site: HDLBits

批量重命名文件

1 2 3 4 5 6 7 8 9 #!/usr/bin/python # -*- coding: UTF-8 -*- import os import re for old_name in os.listdir(path='./'): new_name = re.sub(r'-min', "", old_name) os.rename(old_name, new_name)