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| // 10010
module seq_det(
input clk, rst,
input seq_data,
output reg flag
);
localparam IDLE = 3'b0,
S1 = 3'b1,
S10 = 3'b2,
S100 = 3'b3,
S1001 = 3'b4,
S10010 = 3'b5;
reg [2:0] state, n_state;
always @ (posedge clk or posedge rst)
begin
if (rst)
state <= IDLE;
else
state <= n_state;
end
always @ (*)
begin
n_state = x;
case(state)
IDLE:
begin
if (seq_data==1'b1)
n_state = S1;
else
n_state = IDLE;
end
S1:
begin
if (seq_data==1'b0)
n_state = S10;
else
n_state = S1;
end
S10:
begin
if (seq_data==1'b0)
n_state = S100;
else
n_state = S1;
end
S100:
begin
if (seq_data==1'b1)
n_state = S1001;
else
n_state = IDLE;
end
S1001:
begin
if (seq_data==1'b0)
n_state = S10010;
else
n_state = S1;
end
S10010:
begin
if (seq_data==1'b0)
n_state = S100;
else
n_state = S1;
end
default: ;
endcase
end
always @ (posedge clk or negedge rst)
begin
if (rst)
flag <= 1'b0;
else
begin
case(n_state)
S10010: flag <= 1'b1;
default: ;
endcase
end
end
endmodule
|
